| 胡宏梅.基于VHDL语言的数字钟层次化设计与实现[J].电气自动化,2016,(1):113~115 |
| 基于VHDL语言的数字钟层次化设计与实现 |
| Hierarchical Design and Implementation of a Digital Clock Based on VHDL Language |
| 修订日期：2015-05-26 |
| DOI： |
| 中文关键词: EDA技术 VHDL语言 数字钟 逻辑电路图 层次化设计 |
| 英文关键词:EDA technology VHDL language digital clock logic circuit diagram hierarchical design |
| 基金项目: |
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| 摘要点击次数: 2612 |
| 全文下载次数: 2924 |
| 中文摘要: |
| EDA技术的关键就是用硬件描述语言来描述数字系统,简化了数字系统的设计过程。利用VHDL语言描述数字钟系统,采用自顶向下的方式设计,详述了数字钟底层文件中每个模块的设计思路,及顶层文件的生成,并通过下载仿真,最终实现了系统的设计,具有一定的可行性。 |
| 英文摘要: |
| One of the keys to EDA technology is to use a hardware description language (HDL) to describe the digital system, thus simplifying the design process of the digital system. VHDL is used to describe the digital clock system, and the design is completed in the top-down method. This paper describes in detail the design thought for each module in the bottom document of the digital clock as well as the generation of the top document. After downloading and emulation, the design of the system is completed finally. It has a certain reference value and is feasible to some extent. |
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